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|ca0dd19f||tuexen||Dec. 28, 2021, 8:40 a.m.||sctp: check that the computed frag point is a multiple of 4
Reported by: firstname.lastname@example.org MFC after: 3 dayscgit
|c7f93ee5||adrian||Dec. 28, 2021, 2:33 a.m.||ipq4018_usb_phy: remove old debugging routine
This isn't needed anymore, I know that these work!cgit
|777963af||adrian||Dec. 28, 2021, 2:25 a.m.||qcom_dwc3: add initial Qualcomm SoC DWC3 controller glue
This adds some very simple DWC3 glue for the IPQ4018/IPQ4019. Other chipsets introduce reset line iteration, some further clock line iteration and some customisations; I'll look at adding those later. This is enough to finally bring up USB 3.0 on my IPQ4018 ASUS RT-58U router.cgit
|86f0c3ec||adrian||Dec. 28, 2021, 2:21 a.m.||ipq4018_usb_phy: add USB 2.0 and 3.0 PHY support
This adds the USB 2.0 and 3.0 PHY support for the IPQ4018/IPQ4019. All it really needs to do is gate the relevant clocks on/off in the right order with the right delays.cgit
|f4bf48c2||mav||Dec. 28, 2021, 2:01 a.m.||GEOM: Minor polishing in geom_event.
- Remove timeouts from msleep()'s. Those should always be woken up. - Move wakeup() under the lock to not call on possibly freed pointer. - Remove some dead code. MFC after: 2 weekscgit
|e161dfa9||alc||Dec. 28, 2021, 1:17 a.m.||Fix pmap_is_prefaultable() on arm64 and riscv
The current implementations never correctly return TRUE. In all cases, when they currently return TRUE, they should have returned FALSE. And, in some cases, when they currently return FALSE, they should have returned TRUE. Except for its effects on performance, specifically, additional page faults and pointless calls to pmap_enter_quick() that abort, this error is harmless. That is why it has gone unnoticed. Add a comment to the amd64, arm64, and riscv implementations describing how their return values are computed. Reviewed by: kib, markj MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D33659cgit
|23ba59fb||kib||Dec. 28, 2021, 1:02 a.m.||itimers: strip unused bits from struct itimer and struct itimers|
|3f157084||kib||Dec. 28, 2021, 1:02 a.m.||itimers_alloc: no need to initialize its_timers array|
|0af4ce45||glebius||Dec. 28, 2021, 12:58 a.m.||tcp_usr_shutdown: don't cast inp_ppcb to tcpcb before checking inp_flags
|d11f81af||adrian||Dec. 27, 2021, 11:56 p.m.||qcom_tcsr: add initial top control and status register (TCSR) support
The Qualcomm TCSR is some top level glue between multiple IP blocks, both for doing configuration of said IP blocks, some IPC between them (mostly between multiple execution environments - eg trustzone and non-TZ), and interrupt status bits for them. However, for the IPQ4018/IPQ4019, it only is used as a small subset of IP block configuration. As for what it actually gets used as for other Qualcomm chipsets? Well, that'll have to wait. It's a bit of a mess in linux and openwrt. See, every different SoC support branch ends up with some different TCSR code for it. So instead, I'm going to land a single TCSR driver that I'm going to use for the IPQ4018/IPQ4019. When I add the next chipset, I'll figure out how to organise things so there's a single TCSR driver that works for multiple platforms.cgit
|d27ba308||adrian||Dec. 27, 2021, 11:27 p.m.||qcom_qup: add initial v1/v2 QUP SPI driver
The Qualcomm Universal Peripherals Engine (QUP) is a unified SPI and I2C peripheral that ships with a variety of Qualcomm SoCs. It supports three transfer modes - single PIO, block PIO and DMA. This driver only supports the single PIO mode, which is enough to bootstrap the rest of the SPI NAND/NOR support and means I can do things like read the Wifi calibration data from NOR. It has some hardware support code for the other transfer modes as well as some support for split transfers (ie, transfers with no read or write phase), but I haven't yet implemented those. This driver is based on four sources - the linux driver, the u-boot driver, some initial work done for APQ8064 by mmel@, and the APQ8064 Technical Reference Manual which is surprisingly free and open to read. The linux and u-boot drivers approach a variety of things completely differently, from how PIO is done, the hardware support for re-ordering bytes in a transfer word and how the CS lines are used. Tested: * IPQ4018, SPI to NAND/NOR flash, PIO onlycgit
|989453da||tuexen||Dec. 27, 2021, 10:40 p.m.||sctp: cleanup the SCTP_MAXSEG socket option.
This patch makes the handling of the SCTP_MAXSEG socket option compliant with RFC 6458 (SCTP socket API) and fixes an issue found by syzkaller. Reported by: email@example.com MFC after: 3 dayscgit
|7b36da48||adrian||Dec. 27, 2021, 9:13 p.m.||qca: add cpufreq into the build
Now that the clock drivers are in the tree, the cpufreq driver will "just work". Tested: * IPQ4018, testing performance of dd from /dev/zero->/dev/null at each frequency step.cgit
|cd32ac64||adrian||Dec. 27, 2021, 9:02 p.m.||Add support for qualcomm clock nodes the the IPQ4018/IPQ4019 clock tree.|
|e34a491b||adrian||Dec. 27, 2021, 9:02 p.m.||qcom_clk: add the qualcomm clock nodes for the IPQ4018
These clock nodes are used by the IPQ4018/IPQ4019 and derivatives. They're also used by other 32 and 64 bit qualcomm parts; so it's best to put these nodes here in a single qcom_clk driver and add to it as we grow new Qualcomm SoC support. Tested: * IPQ4018, boot Differential Revision: https://reviews.freebsd.org/D33665cgit