r366048 bdragon Sept. 23, 2020, 1:41 a.m.
Not much to say here, another missing be64toh() in memory that was written
from OPAL.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366047 bdragon Sept. 23, 2020, 1:37 a.m.
Since OPAL runs in big endian, any data being passed back and forth
via memory instead of registers needs to be byteswapped.

From my notes during development:

"A good way to find candidates is to look for vtophys() in opal_call()
parameters. The memory being passed will be written into in BE."

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366046 bdragon Sept. 23, 2020, 1:33 a.m.
It's much easier to implement this in an endian-independent way when we
don't also have to worry about masking half of the dword off.

Given that this code ran on a machine that ran a poudriere bulk with no
kernel oddities, I am relatively certain it is correctly implemented. ;)

This should be a minor performance boost on BE as well.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366045 bdragon Sept. 23, 2020, 1:29 a.m.
For a body of code that had its endian conversion bits written blind without
the ability to test, moea64 was VERY close to being correct.

There were only four instances where the existing code was getting it wrong.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366044 bdragon Sept. 23, 2020, 1:13 a.m.
This was originally part of the initial commit, but after discussion in
D26399, I split it out into its own commit after the kernel config file.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366043 bdragon Sept. 23, 2020, 1:07 a.m.
This is slightly stripped down from GENERIC64, as PowerMac G5 machines
are incapable of running in LE mode (so we can skip the Mac drivers.)

While technically POWER6 and POWER7 have the hardware capability of running
in LE mode, they have a tendency to trap excessively when a load/store is
misaligned. (an extremely common occurrence in LE code, and one of the main
reasons I consider BE to be superior, as it turns potential security issues
into immediately obvious mangled numbers.)

Additionally, there was no mechanism to control what endian interrupts
are delivered in, so supporting LE operation on POWER6 and POWER7 involves
some really dirty tricks in the interrupt vectors that I would rather
avoid.

IBM drew the line in the sand at POWER8 some time around 2013, embracing
full support for LE in the platform, and making a push across the board
for LE code to target POWER8 as a minimum requirement. As such, usage of
LE kernels on POWER6 and POWER7 is practically nil, despite it being
technically possible to do.

The so-called "TRUELE" feature bit which is the baseline requirement for
 needed for PowerPC64LE was introduced in POWER8.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366042 imp Sept. 23, 2020, 1:04 a.m.
There was a small window cp was broken. Work around this by using :>
instead of cp /dev/null. Ideally, we'd keep the cp /dev/null in the
build as a regression test, but doing so breaks people that upgraded
during the cp breakage and this is simpler than bootstrapping a
working cp since there's no good __FreeBSD_version sign posts for
that.

Suggested by: lots of people
Too stubborn for his own good: imp
ViewVC
r366041 bdragon Sept. 23, 2020, 12:32 a.m.
When running without a hypervisor, we need to set the ILE bit in the LPCR
ourselves.

For the boot processor, handle it in powernv_attach() like we do for other
LPCR bits.

No change for the APs, as they will use the lpcr global to set up their own
LPCR when they do their own cpudep_ap_early_bootstrap() and pick up this
automatically.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366040 bdragon Sept. 23, 2020, 12:28 a.m.
OPAL runs in big endian, so we need to rfid into it to switch endian
atomically when branching to it, and we need to do the
RETURN_TO_NATIVE_ENDIAN dance when it returns to us.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366039 bdragon Sept. 23, 2020, 12:21 a.m.
Given that we have converted to ELFv2 for BE already, endianness is the only
difference between the two ARCHs.

As such, there is no need to differentiate LIBC_ARCH between the two.

Combining them like this lets us avoid needing to have two copies of several
bits for no good reason.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366038 bdragon Sept. 23, 2020, 12:13 a.m.
Unlike virtio, which in legacy mode is guest endian, the hypervisor vscsi
interface operates in big endian, so we must convert back and forth in several
places.

These changes are enough to attach a rootdisk.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366037 bdragon Sept. 23, 2020, 12:09 a.m.
The TCG implementation of mtmsrd in qemu blindly copies the entire register
to the MSR, instead of the specific bit positions listed in the ISA.

This means that qemu will prematurely switch endian out from under the
running code instead of waiting for the rfid, causing an immediate trap
as it attempts to interpret the next instruction in the wrong endianness.

To work around this, ensure PSL_LE is still set before doing the mtmsrd.

In the future, we may wish to just turn off translation and unconditionally
use rfid to switch to the ofmsr instead of quasi-switching to the ofmsr.

Add a new platform option so this can be disabled. (And so that we can
conditonalize additional QEMU-specific hacks in the platform code.)

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366036 bdragon Sept. 23, 2020, 12:06 a.m.
This applies to both pseries and powernv, which were tested at different
points during the patchset development.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366035 bdragon Sept. 23, 2020, 12:03 a.m.
Since we will need to be able to take traps relatively early in the process,
ensure that the hypervisor changes our ILE for us as soon as we are ready.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC
r366034 bdragon Sept. 22, 2020, 11:59 p.m.
Since OFW always runs in big endian in practice, we need to convert several
bits back and forth.

This is necessary to communicate with SLOF on LE pseries.

Sponsored by:	Tag1 Consulting, Inc.
ViewVC