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|r354719||mhorne||Nov. 15, 2019, 3:22 a.m.||RISC-V: pass arg6 in sbi_call
Allow for an additional argument to sbi_call which will be passed in a6. This is required for SBI spec 0.2 support, as a6 will indicate the SBI function ID. While here, introduce some macros to clean up the calls. Reviewed by: kp, jhb MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D22325ViewVC
|r354718||mhorne||Nov. 15, 2019, 3:18 a.m.||plic: support irq distribution
Our PLIC implementation only enables interrupts on the boot cpu. Implement plic_bind_intr() so that they can be redistributed near the end of boot during intr_irq_shuffle(). This also slightly modifies how enable bits are handled in an attempt to better fit the PIC interface. plic_enable_intr()/plic_disable_intr() are converted to manage an interrupt source's threshold value, since this value can be used as to globally enable/disable an irq. All handing of the per-context enable bits is moved to the new methods plic_setup_intr() and plic_bind_intr(). Reviewed by: br MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D21928ViewVC
|r354717||mhorne||Nov. 15, 2019, 3:15 a.m.||plic: fix context calculation
The RISC-V PLIC (platform level interrupt controller) registers are divided up by "context", which is purposefully left ambiguous in the PLIC spec. Currently we assume each CPU number corresponds 1-to-1 with a context number, but that is not correct. Most existing PLIC implementations (such as SiFive's) have multiple contexts per-cpu. For example, a single CPU might have a context for machine mode interrupts and a context for supervisor mode interrupts. To complicate things further, FreeBSD renumbers the CPUs during boot, but the PLIC driver still assumes that CPU ID equals the RISC-V hart number, meaning interrupt enables/claims might be performed for the wrong context registers. To fix this, we must calculate each CPU's context number during attachment. This is done by reading the interrupt properties from the device tree, from which a mapping from context to RISC-V hart to CPU number can be created. Reviewed by: br MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D21927ViewVC
|r354716||jpaetzel||Nov. 15, 2019, 1:07 a.m.||Fix build with GCC
Fix suggested by: jhb, scottl Sponsored by: PanzuraViewVC
|r354715||jpaetzel||Nov. 14, 2019, 11:31 p.m.||Add the pvscsi driver to the tree.
This driver allows to usage of the paravirt SCSI controller in VMware products like ESXi. The pvscsi driver provides a substantial performance improvement in block devices versus the emulated mpt and mps SCSI/SAS controllers. Error handling in this driver has not been extensively tested yet. Submitted by: email@example.com Relnotes: yes Sponsored by: VMware, Panzura Differential Revision: D18613ViewVC
|r354714||jhibbits||Nov. 14, 2019, 9:58 p.m.||Boot arm64 kernel using booti command from U-boot.
Summary: Boot arm64 kernel using booti command from U-boot. booti can relocate initrd image into higher ram addresses, therefore align the initrd load address to 1GiB and create VA = PA map for it. Create L2 pagetable entries to copy the initrd image into KVA. (parts of the code in https://reviews.freebsd.org/D13861 was referred and used as appropriate) Submitted by: Siddharth Tuli <siddharthtuli_gmail.com> Reviewed by: manu Sponsored by: Juniper Networks, Inc Differential Revision: https://reviews.freebsd.org/D22255ViewVC
|r354713||bdragon||Nov. 14, 2019, 7:56 p.m.||[PowerPC64] Fix broken kernel modules due to LLD 9+ TOC optimization
LLD9 introduced a TOC optimization that isn't compatible with kernel dynamic linker causing panic when loading kernel modules (pf, linuxkpi etc.) This patch disables TOC optimization when building kernel modules. Submitted by: Alfredo Dal'Ava Junior <firstname.lastname@example.org> Approved by: jhibbits (mentor) Differential Revision: https://reviews.freebsd.org/D22317ViewVC
|r354712||kevans||Nov. 14, 2019, 6:38 p.m.||arm64: busdma_bounce: fix BUS_DMA_ALLOCNOW for non-paged aligned sizes
For any size that isn't page-aligned, we end up not pre-allocating enough for a single mapping because we truncate the size instead of rounding up to make sure the last bit is accounted for, leaving us one page shy of what we need to fulfill a request. Differential Revision: https://reviews.freebsd.org/D22288ViewVC
|r354711||brooks||Nov. 14, 2019, 5:11 p.m.||Tidy syscall declerations.|
|r354710||ian||Nov. 14, 2019, 5:04 p.m.||Compile in arm/unwind.c if options STACK is in effect; the new arm stack(9)
code now uses unwind.c.ViewVC
|r354709||ian||Nov. 14, 2019, 4:46 p.m.||Rewrite arm/stack_machdep.c for EABI; add stack(9) support to arm kernels.
The old stack_machdep.c code was written for the APCS ABI (aka "oldabi"). When we switched to ARM EABI (back in freebsd 10) this file never got updated, and apparently nobody noticed that until now. The new implementation uses the same stack unwinder code used by the arm implemenation of the db_trace stuff.ViewVC
|r354708||tuexen||Nov. 14, 2019, 4:28 p.m.||For idle TCP sessions using the CUBIC congestio control, reset ssthresh|
|r354707||emaste||Nov. 14, 2019, 3:10 p.m.||llvm: use elf_aux_info to get executable's path, if available
Obtained from: LLVM a0a38b81ea MFC with: r354692 Sponsored by: The FreeBSD FoundationViewVC
|r354703||mav||Nov. 14, 2019, 4:39 a.m.||Pass more reasonable WAIT flags to bus_dma(9) calls.
MFC after: 2 weeksViewVC
|r354702||mav||Nov. 14, 2019, 4:34 a.m.||Make ntb(4) send bus_get_dma_tag() requests to parent buses passing real
bus' child pointers instead of grandchilds. DMAR does not like requests from devices not parented directly by PCI. MFC after: 2 weeksViewVC